Coordinates the courses: Reconfigurable Computing
Coordinates the laboratories: Electronic Circuits (Digital), Project 2
Active in the projects: A method for the differential diagnosis of meningitis by determining the cytokine profile using a rapid measurement device at point of care , Assistance System for Intelligent Buildings Controlled by Voice and Natural Speech, Noise-Robust, Domain-Adaptable, Large-Vocabulary Automatic Speech Recognition System for the Romanian Language
Publications
2018
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, "Dynamically changing the secret key of an FPGA chaos-based cipher", ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, Vol. 21, pp. 18-33, Publisher: EDITURA ACAD ROMANE, WOS:000433876800002, 2018, [Article]
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, "FPGA optimized cellular automaton random number generator", JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, Vol. 111, pp. 251-259, Publisher: ACADEMIC PRESS INC ELSEVIER SCIENCE, WOS:000415028900019, DOI:10.1016/j.jpdc.2017.05.022, 2018, [Article]
2017
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, "Baptista's Chaos-Based Cipher Implemented in a Field Programmable Gate Array", 2017 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), 40TH EDITION, pp. 191-194, Publisher: IEEE, WOS:000425844500040, 2017, [Proceedings Paper]
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, "EVALUATION OF A LOW-POWER HADOOP CLUSTER BASED ON THE ZYNQ ARM-FPGA SOC", UNIVERSITY POLITEHNICA OF BUCHAREST SCIENTIFIC BULLETIN SERIES C-ELECTRICAL ENGINEERING AND COMPUTER SCIENCE, Vol. 79, pp. 125-136, Publisher: POLYTECHNIC UNIV BUCHAREST, WOS:000405770100010, 2017, [Article]
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, "FPGA systolic array GZIP compressor", PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON ELECTRONICS, COMPUTERS AND ARTIFICIAL INTELLIGENCE - ECAI 2017, Publisher: IEEE, WOS:000425865900003, 2017, [Proceedings Paper]
2016
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, "An evaluation of low-power microphone array sound source localization for deforestation detection", Applied Acoustics, Volume 113, , pp. 162–169, Publisher: Elsevier, None, 2016, [None]
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, "A SOFTWARE-DEFINED FPGA VECTOR PROCESSOR WITH APPLICATION-AWARE RECONFIGURATION", UNIVERSITY POLITEHNICA OF BUCHAREST SCIENTIFIC BULLETIN SERIES C-ELECTRICAL ENGINEERING AND COMPUTER SCIENCE, Vol. 78, pp. 43-56, Publisher: POLYTECHNIC UNIV BUCHAREST, WOS:000393328400004, 2016, [Article]
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, "Efficient Implementation of a Video Change Detection Algorithm", 2016 INTERNATIONAL CONFERENCE ON COMMUNICATIONS (COMM 2016), pp. 77-82, Publisher: IEEE, WOS:000383221900017, 2016, [Proceedings Paper]
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, "Global Feedback Self-Programmable Cellular Automaton Random Number Generator", Revista Tecnica De La Facultad De Ingenieria Universidad Del Zulia, , Vol. 39, pp. 1-9, , DOI:10.21311/001.39.1.01, 2016, [Article]
2015
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, "Hybrid Adaptive Clock Management for FPGA Processor Acceleration", 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), pp. 1359-1364, Publisher: IEEE, WOS:000380393200255, 2015, [Proceedings Paper]
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, "IxFIZZ: Integrated Functional and Fuzz Testing Framework based on Sulley and SPIN", ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, Vol. 18, pp. 54-68, Publisher: EDITURA ACAD ROMANE, WOS:000369852700004, 2015, [Article]
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, "Energy-Efficient WSN Architecture for Illegal Deforestation Detection", International Journal of Sensors and Sensor Networks, Volume 3, Issue 3, , pp. 24-30, Publisher: Science Publishing Group, None, 2015, [None]
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, "Hybrid Adaptive Clock Management for FPGA Processor Acceleration",
Design, Automation and Test in Europe (DATE)
, pp. 1359-1364, Publisher: EDA Consortium, None, 2015, [None] -
, "IxFIZZ: Integrated Functional and Fuzz Testing Framework based on Sulley and SPIN", Romanian Journal of Information Science and Technology, Volume 18, Issue 1, , pp. 54-68, None, 2015, [None]
2014
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, "An Automatic Speech Recognition Solution with Speaker Identification Support", 2014 10TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS (COMM), Publisher: IEEE, WOS:000345844600018, 2014, [Proceedings Paper]
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, "Cellular Automaton pRNG with a Global Loop for Non-Uniform Rule Control", 18th International Conference on Circuits, Systems, Communications and Computers (CSCC), Vol. 2, pp. 415-420, , 2014, [Proceedings Paper]
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, "Energy-Efficient Computation of L1 and L2 Norms on a FPGA SIMD Accelerator, with Applications to Visual Search", 18th International Conference on Circuits, Systems, Communications and Computers (CSCC), Vol. 2, pp. 432-437, , 2014, [Proceedings Paper]
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, "An Automatic Speech Recognition Solution with Speaker Identification Support",
10th International Conference on Communications (COMM)
, , 2014, [] -
, "A Robust Diacritics Restoration System using Unreliable Raw Text Data",
4th International Workshop on Spoken Language Technologies for Under-Resourced Languages (SLTU)
, None, 2014, [None] -
, "Recent Improvements of the SpeeD Romanian LVCSR System", 2014 10TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS (COMM), Publisher: IEEE, WOS:000345844600003, 2014, [Proceedings Paper]
2013
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, "Cognitive Radio Testing Framework Based on USRP", 2013 21ST TELECOMMUNICATIONS FORUM (TELFOR), pp. 212, Publisher: IEEE, WOS:000349857500052, 2013, [Proceedings Paper]
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, "OPINCAA: A Light-Weight and Flexible Programming Environment For Parallel SIMD Accelerators", ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, Vol. 16, pp. 336-350, Publisher: EDITURA ACAD ROMANE, WOS:000336723900006, 2013, [Article]
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, "Cognitive Radio Testing Framework based on USRP",
21st Telecommunications Forum (TELFOR)
, pp. 212-215, None, 2013, [None] -
, "VASILE: A Reconfigurable Vector Architecture for Instruction Level Frequency Scaling",
Faible Tension Faible Consommation (FTFC)
, None, 2013, [None] -
, "VASILE: A Reconfigurable Vector Architecture for Instruction Level Frequency Scaling", 2013 IEEE FAIBLE TENSION FAIBLE CONSOMMATION (FTFC), Publisher: IEEE, WOS:000332574000026, 2013, [Proceedings Paper]
2012
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, "A SIMD Approach to Thread Matching for Interleaved Multithreading", ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, Vol. 15, pp. 215-228, Publisher: EDITURA ACAD ROMANE, WOS:000323705800002, 2012, [Article]
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, "Dynamic Power Management Through Adaptive Task Scheduling for Multi-Threaded SIMD Processors", 2012 10TH INTERNATIONAL SYMPOSIUM ON ELECTRONICS AND TELECOMMUNICATIONS, pp. 83-86, Publisher: IEEE, WOS:000318702700019, 2012, [Proceedings Paper]
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, "GNU COMPILER COLLECTION BACKEND PORT FOR THE INTEGRAL PARALLEL ARCHITECTURE", UNIVERSITY POLITEHNICA OF BUCHAREST SCIENTIFIC BULLETIN SERIES C-ELECTRICAL ENGINEERING AND COMPUTER SCIENCE, Vol. 74, pp. 79-92, , 2012, [Article]
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, "A SIMD Approach to Thread Matching for Interleaved Multithreading",
Romanian Journal of Information Science and Technology
, pp. 215-228, None, 2012, [None] -
, "Dynamic Power Management through Adaptive Task Scheduling for Multi-Threaded SIMD Processors",
10th International Symposium on Electronics and Telecommunications (ISETC)
, pp. 83-86, None, 2012, [None]
2011
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, "Increasing vector processor pipeline efficiency with a thread-interleaved controller", 15th International Conference on System Theory, Control, and Computing (ICSTCC), , Vol. 1, pp. 1 - 4, Publisher: IEEE, None, 2011, [Proceeding paper]
2010
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, "Integral Parallel Architecture in System-on-Chip Designs",
CAS 2010 Proceedings, vol.1
, pp. 35-42, None, 2010, [None] -
, "TECHNOLOGY DRIVEN ARCHITECTURE FOR INTEGRAL PARALLEL EMBEDDED COMPUTING", 2010 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), VOLS 1 AND 2, pp. 35-42, Publisher: IEEE, WOS:000371396100005, 2010, [Proceedings Paper]
Degrees
- PhD Degree, in Electronics and Telecommunication (Oct 2012), University “Politehnica” of Bucharest.
- Engineer Degree, in Microelectronics (June 2009), University “Politehnica” of Bucharest.
Professional Experience
Assistant Professor (2014-Present), with the DCAE Department
Teaching Assistant (2009-2014), with the DCAE Department of the Faculty of Electronics, University POLITEHNICA of Bucharest
Research Intern (2011-2012), at Ixia LLC
Visiting Researcher (2010-2011) , Technical University of Delft, the Netherlands, Mathematics and Computer Science Department
FPGA Digital Circuit Design Engineer (2008-2009), Ixia LLC
Digital Circuit Design Engineer (2007-2009), UbiCore Technologies SRL
Academic Activity
My research interests cover a broad area of computer-related technologies, from application-specific integrated circuits (ASICs) to reconfigurable computing with FPGAs, compilers and programming technologies, and parallel computing applications. I take special interest in heterogeneous low-energy computing solutions for both embedded platforms and high-performance distributed computing.