Computer Architecture
Coordinated by: Zoltan Hascsi
Description:
The Computer Architecture laboratory introduces the students the architecture of a basic 32-bit RISC processor. Starting from the functional specification provided by the professor, the students are guided to define the processor's internal architecture at module level, and then implement the modules using Verilog HDL and the Xilinx ISE suite (simulator and synthesis).
Other department members involved in this laboratory: Mihai Antonescu