Demonstrator Fabrication in Planar Technology of a Tunneling Transistor through Ultra-thin Insulators - A Promotor of a Nanodevices Series and Industrial Usefulness Emphasis
Coordinated by: Cristian Ravariu
Other persons involved in the project
- CP I Elena Manea
- CP I Purica Munizer
- CP I Ileana Cernica
- CP I Adrian Dinescu
- CP II Ioana Pachiu
- Resp. econ. Alina Popescu
- CP III Cătălin Pârvulescu
- Drd. Vlad Plăcintă
UEFISCDI Code: PN-III- P2-2.1- PED-2016- 0427
Project type: Experimental Demonstrative Project
Contract no: 205PED / 2017
Period: August 2017 - December 2018
Abstract: The main objective of this project is the fabrication of an electronic device prototype based on the ultra-thin insulator tunneling, as the first exponent on Silicon wafer of the so called Nothing On Insulator (NOI) transistor, as planar variant. For p-NOI, the insulator can be vacuum or oxide and is important to be ultra-thin of 2...10nm thickness. We propose in this project a planar p-NOI architecture, achievable in the Si-technology, with oxide as insulator. The practical relevance of the project derives from a fabricated p-NOI device in multiple variants and the matching between experimental, theoretical and simulated curves. So that the future Atlas simulations to be anchored in a real technology. This obvious step of a p-NOI exponent fabrication was clearly demanded by the last reviewers from IEEE Transaction on Electron Devices and VLSI. The technical-scientific novelty and feasibility derive from: new device implementation by a well-controlled Si- planar technology, preliminary p-NOI variant already simulated in Atlas in this proposal and intermediary steps in the project plan (masks design and simulations, masks fabrication ~ intermediary steps for fabrication). The project management concerns the product management scheme.The experience of both teams - UPB- IMT, also demonstrated in previous common research projects and publishing, is a favorable reason to ensure the project scope and feasibility.
O1. Design and simulation of the NOI variants, in different configurations;
O2. Design of the technology for the p-NOI variants implementations in Si-planar technology;
O3. Masks design & fabrication for p-NOI variants on Si-wafer;
O4. Fabrication of the p-NOI variants in the Si-planar technology;
O5. Electrical tests and characterization of p-NOI fabricated variants;
O6. Demonstration the ID-VD tunneling in fabricated p-NOI, by experimental measurements;
O7. Searching for industrial applications, patent, formulation of conclusions;
O8. Disseminations, technical meetings.
Scientific results per project
- selection of p-NOI device variants to be constructed in Si-planar technology;
- functional validation by Atlas-Athena simulations;
- designing of the technological steps and masks for p-NOI;
- production of the p-NOI masks set.
- the practical result of the technological flow in Silicon for p-NOI variants;
- practical products made as variants of p-NOI (NOI in planar technology);
- the material and process characterization results;
- the static and dynamic characterizations of manufactured p-NOI results;
- financial and scientific reports per steps;
- results as published articles and dissemination in national / international scientific forums;
- submission of 1 patent to OSIM.
- Stage I. Design and simulation of the p-NOI variants aided by soft-hard tools
- Stage II. Fabrication of the p-NOI variants, assisted by microelectronics tools from Si-technology
Results for the DEMOTUN project at Stage I / 2017:
(i) selection of p-NOI variants to be constructed in planar technology;
(ii) p-NOI simulations in Athena as technology and functional validations through Atlas simulations;
(iii) designing the technological steps for making p-NOI variants;
(iv) designing the p-NOI mask set with EDA LEDIT simulator;
(v) producing the set of masks with the IMT facilities for the p-NOI variants.
Results in the form of measurements, products, simulations at Stage I/2017
Fig. 1. (a) Designing the two Planar-NOI structures that we can develop as demonstrators; (b) experimental reference demonstration in literature, which attests the gate tunnel current through the last generation of MOSFET; (c) preliminary simulation of the NOI transistor on Si; (d) extracted characteristics ID-VG.
Fig. 2. (a) Demonstration of formation of triangular potential barrier, and thus subject to the Fowler-Nordheim law and for NOI structures with Oxide instead of vacuum, (b) Design of technology - Initially doped substrate with Phosphorus 1e14 coated with a layer of oxide; (c) advanced technological steps; (d) design - masks design at IMT.
Publishing-dissemination activities in 2017
In the implementation plan, for the I stage, we have committed to the management / dissemination results: minimum 2 project meetings, economic support and procurement, drafting the economic and scientific report of Co and Global and publications, eventual publications.
Articles minimum 1 in ISI Journal/Conference
In 2017, the following ISI indexed items were published:
1. C. Ravariu, E. Manea, F. Babarada, Masks and metallic electrode compounds for silicon biosensor integration, Journal of Alloys and Compounds, Elsevier, 2017, vol 697, pp. 72-79, March 2017, WOS: 000391820800012 , DOI 10.1016 / j.jallcom.2016.12.099, where Acknowledgement with DEMOTUN contract 205PED / 2017, PN-III-PED-DEMOTUN 2016 is mentioned in the Acknowledgement with partial contribution. Awarded the Red Zone by UEFISCDI in Oct. 2017.
Conference papers: 2 ISIs and 2 BDIs
In 2017, the following items were published that are not indexed securely based on ISI but are present in other BDI databases:
1. Cristian Ravariu, Dan Mihaiescu, Static and dynamic aspects of different tunneling of NOI nanotransistors with oxid and vacuum, in Proceedings of European Conference on Electrical Engineering and Computer Science, Bern, Switzerland, 17-19 Nov. 2017, pp. 1-4, Indexed IEEE in 2018, Project - PED mentioned partial contribution to Acknowledgement.
2. C. Ravariu, D. Mihaiescu, F. Babarada, E. Manea, M. Idu, L. Vladoianu, Vertical Variants of PIN and p-NOI Tunnel Electronic Devices and Potential Applications, 5th International IEEE Symposium on Electrical and Electronics Engineering , Galati, Romania, Oct. 20-22, 2017, pp.36.1-36.6, ID_Paper61, Section Oral, Proceedings ISBN 978-1-5386-2059-5 / 17 / $ 31.00 @ 2017 IEEE, indexed IEEE, Project - PED mentioned for total contribution to Acknowledgment, indexed ISI cu WOS:000428234400050.
3. C. Ravariu, F. Babarada; Resizing and Reshaping of the Nothing On Insulator NOI Transistor; Advanced Nano-Bio-Materials and Devices; 2017, vol.1, issue 1, pp. 18-23, ISSN 2559-1118, SciEdTech EU Platform, in connection with the PED project.
4. V. M. Placinta, L. N. Cojocariu, C. Ravariu, Evaluation of the Switching Mode Power Supplies used in Radiation Hardness Tests of Integrated Circuits, in Proc. of the 40th edition of IEEE International Semiconductor Conference CAS'2017, Oct. 11-14, Sinaia, Romania, p.1-4, Oral, regarding the PED project, indexed ISI cu WOS:000425844500068.
Preparing 1 book chapter at the international publishing house
1. Cristian Ravariu, Elena Manea, Alina Popescu, Catalin Pîrvulescu, Integrated p-NOI structures within a biosensor with nanoporous layer, for environment monitoring, Chapter in Book: Green Electronics, In-Tech Publisher House (Croatia-Austria), ISBN: 978-953-51-6075-5, accepted in Nov. 2017, in press for 2018, Project - PED at Acknowledgement.
Preparation 1 patent proposal
A patent proposal on implementing solutions for p-NO structures has been prepared. Subsequently, in 2018, the application was actually filed with OSIM.
Meetings on the project
There have been at least 2 meetings per project, meaning that there were 2 main meetings, with more participants and minutes, and 2 more meetings on sub-groups during Phase I.
Results for the DEMOTUN project at Stage II / 2018:
(i) results of p-NOI conduction simulations;
(ii) the result of the technological flow in Silicon for making p-NOI;
(iii) products as variants of p-NOI (NOI in planar technology);
(iv) results of material and process characterization; the results of the electronic measurements of p-NOI devices;
(v) results of possible applications of NOI devices in general;
(vi) financial and scientific reports per stage submitted to UEFISCDI;
(vii) results in the form of articles published in national / international scientific forums;
(viii) the result of filing 1 patent in OSIM.
Results in the form of measurements, products, simulations at Stage II/2018
(a) (b) (c) (d)
Fig. 1. (a) P-NOI4 structure polarized at + 29V; (b) The p-NOI3 structure polarized at + 29V; (c) Current vectors with the polarized p-NOI5 structure; (d) Current vectors of the polarized p-NOI6 structure.
Fig. 2. (a) Current-voltage characteristics of the p-NOI4 structure; (b) The substrate current to the p-NOI5 transistor polarized at Vd = 1 and then Vd = 9V; (c) the source current when varying the gate voltage, demonstrating also the operation of the p-NOI side device of p-NOI6; (d) the current through the source, when an increasing voltage is applied to the source, demonstrating that the tunneling from the source to the substrate.
Fig. 3. (a) The p-NOI8 structure polarized at 0V on the face and -130V on the substrate; (b) IG-VG for p-NOI with various oxide thicknesses; (c) study of metal semiconductor replacement by simulating the operation of the polarized p-NOI-MIM transistor at VDS = 6V, VG = -1V; (d) comparisons between the characteristics of the various p-NOI variants.
Fig. 4. (a) P-NOI device with 1nm-SiO2 / 4nm-HfO2; (b) the IG-VG characteristic for various thicknesses of insulators, and comparison with experimental points; (c) Masks of IMT configured by EBL; (d) experimental characterization probe purchased.
Publishing-dissemination activities in 2018
In the implementation plan, for the this stage, we have committed to the management / dissemination results: writing the required reports in stage 2, dissemination by publishing articles, filing a patent at OSIM, organizing the project meetings, organizing the workshop through the collaboration with IEEE-SSCS-ED Chapter; national or international publication of the results.
A. Articles ISI Red/yellow zone
In 2018, the following article was published in the journal: IEEE Journal of Electron Device Society (JEDS), which at the time of submitting the article was in the red area, position 56/2017 at Engineering Electrical at more than 10 lines before the border to the yellow area indexing for premiers in 2017 after IF), but the publication took place after Sept. 2018, when the first accepted IEEE article was posted as Early Access Paper with DOI, when the new rankings were posted in 2018, and the JEDS journal is now in position 83 after the IF.
1. C. Ravariu, "Vacuum nano-triode in Nothing-On-Insulator configuration working in Terahertz domain," IEEE Journal of the Electron Devices Society, DECEMBER.2018, Volume: 6 Issue: 1, page(s): 1115-1123, Print ISSN: 2168-6734, DOI: 10.1109/JEDS.2018.2868465, project PN-III-P2-2.1-PED-2016-0427 under Project 205PED/2017-DEMOTUN, IEEE-xplore Early access paper Sept. 2018. On: https://ieeexplore.ieee.org/document/8453784/
B. ISI Journal articles / conferences
In 2018, the following articles were indexed on ISI basis, or included in Conference Proceedings that posted all time on their site that these conferences indexed ISI-Thomson-accepted items, and that they have at Acknowledgments the DEMOTUN project code included.
1. Ravariu Cristian; Manea Elena; Babarada Florin; Ursutiu Doru; Mihaiescu Dan; Popescu Alina, Organic Compounds Integrated on Nanostructured Materials for Biomedical Applications, in Proc. of 15th International Conference on Remote Engineering and Virtual Instrumentation, REV2018, 21-24 March 2018, Duesseldorf, Germany, pp. 600-608, Conference Track: Special Session: Biomedical Engineering, Paper ID 1235, Oral presentation, In Springer, ISI; 2 projecs: 205PED, 4-PCE.
2. C. Ravariu, F. Babarada, D. Mihaiescu, E. Manea, C. Pârvulescu, A. Popescu, Technology of fabrication and functional validations of planar-Nothing On Insulator devices with oxide instead vacuum, ECAI 2018 - International Conference – 10th Edition Electronics, Computers and Artificial Intelligence, 28 June -30 June, 2018, Iasi, ROMANIA, pp. 11 in Abstract book, Oral presentation, 4pages for ISI/ IEEE, 205PED
3. C. Ravariu, F. Babarada, J. Arhip, E. Manea, C. Pârvulescu, Personalized Mio-electrical Monitoring System Based on ADS1298 and MIM Electrodes, ECAI 2018 - International Conference – 10th Edition Electronics, Computers and Artificial Intelligence, 28 June -30 June, 2018, Iasi, ROMANIA, pp. 12 in Abstract book, Oral presentation, 4pages for ISI/ IEEE, 205PED.
4. Cristian Ravariu, Elena Manea, Alina Popescu, Catălin Pârvulescu, Nonlinear Electrical Conduction Theorem - a Valuable Tool for Different Non-linear Systems, 5th International Conference on Mathematics and Computers in Sciences and Industry MCSI-2018, pp. 1-4, Corfu, Grecia, 24-27. 25-27 Aug. 2018, Oral. IEEE/ISI index. 205PED, 4-PCE.
5. Cristian Ravariu, Elena Manea, Catalin Parvulescu, Florin Babarada, Alina Popescu and Avireni Srinivasulu, The Gate Current in MOSFETs versus planar-NOI Devices, IEEE Conference of Semiconductors, Accepted, in press, Oct. 2018. 205PED.
C. Articles in Journals / Conferences BDI
1. Cristian Ravariu, Dan Eduard Mihaiescu, Physical phenomena captured in a mathematical model of p-NOI and NOI transistors, International Journal of Circuits, Systems and Signal Processing, ISSN: 1998-4464, vol. 11, no. Dec., pp. 396-400, (published online in Jan 2018) http://naun.org/cms.action?id=15911, 205PED, PROZECHIMED; index BDI: Scopus, Compendex, Inspec - The IET, Index Copernicus.
2. Cristian Ravariu, Dan Eduard Mihaiescu, Elena Manea, Cătălin Pârvulescu, A Nothing On Insulator - NOI - Nanotransistor Configuration suitable for the Zaidman Model, XX-th International Symposium on Electrical Apparatus and Technologies SIELA 2018, Bourgas, Bulgaria, June 2-6, 2018, Digest, pp. 219-220, Oral presentation, IEEE indexare pp. 1-4, ID18. 205PED, 4-PCE. DOI: 10.1109/SIELA.2018.8447159, Date Added to IEEE Xplore: 27 August 2018.
3. Cătălin Pârvulescu, Cristian Ravariu, Elena Manea, Florin Babarada, Alina Popescu, Beyond SOI - the NOI Nanotransistor - Simulations Results And New Challenges, 15th International Multidisciplinary Modeling & Simulation Multiconference (I3m'2018), In Conjunction With European Modeling And Simulation Symposium (EMSS'2018) event, Budapest, Ungaria 15-19.09. 2018, 205PED, 4-PCE.
4. C. Ravariu, SSCS Romania Chapter Welcomes DL Sorin Voinigescu in 2017, IEEE Solid State Circuit Magazine, Vol. 10, no.1, pp. 59-60, Jan. 2018, DOI 10.1109/MSSC.2017.2769328. (ISSN 1943-0582).
D. Articles - abstract at Conferences
1. Elena Manea, Cristian Ravariu, Catalin Pârvulescu, Florin Babarada, Alina Popescu, Technological methods and concepts of the planar-Nothing On Insulator device, abstract n°9314, 34th International Conference on the Physics of Semiconductors, ICPS-2018, Montpellier, Franta, 29.07-03.08. 2018, POSTER presentation. 205PED.
2. Elena Manea, Cristian Ravariu, Catalin Pârvulescu, Florin Babarada, Alina Popescu, Semiconductor Conference, IEEE CAS'2018, Abstract si Poster in Program.
E. Patent filing OSIM.
Patent application filed with OSIM, with applicant: Polytechnic University of Bucharest - UPB Bucharest, inventors: RAVARIU Cristian, BABARADA Florin, MANEA Elena, PÂRVULESCU CĂTĂlin Corneliu, with the title: "The manufacturing process of the planar semiconductor device for tunnel testing of ultra-thin insulators ", no. registration at OSIM: A / 00526 of 11 July 2018.
F. Organization of project sessions, organization of Workshop through collaboration with IEEE-SSCS-ED Chapter
There have been at least 2 meetings per project, meaning that there were 2 main meetings, with more participants and minutes, and several more meetings on sub-groups during the phase-out (about a 2-week meeting).
Organization of min. 1 Workshop with internal and external participation, i.e. with a foreign expert invited to Romania, was accomplished with the help of the IEEE SSCS037 Chapter, which is the chairman of the project director.
The event was organized by the PCE Project Director no. 4/2017, who is Chairman of the IEEE-Electron Device Society EDS015-Romania and IEEE Solid State Circuits SSCS037-Romania, and IEEE-ECAI Conference Chairpersons and Organizers in 2018, where our event was joined from the first day of the conference, and the key moment of the Workshop was: "Round table, under the auspices project number 205PED / 2017-DEMOTUN and 4/2017-TFTNANOEL, in Iasi, Romania, 28.06.2018, 12:15 - 14:00.
During the workshop, internal members of the PCE project (Cristian Ravariu, Catalin Parvulescu, others) and external (Romanian teachers and specialists, students from all levels of education) and several foreign guests were invited to a lecture by a guest of the IEEE, Senior Member Distinguished Lecturer Prof. Avireni Srinivasulu, Senior Member IEEE, B.Tech, ME, MS, Ph.D. (Birla Institute of Tech. - Mesra), Professor of Electronics and Communication Enggineering, JECRC University, Jaipur, Rajasthan , India. Details for Prof. Avireni Srinivasulu are available at:
The workshop had as a central event the lecture of Professor Srinivasulu entitled "Novel Semiconductor Devices and its Applications in Circuits", followed by lengthy debates, consultations and memorandum.
As an event organized under the main SSCS-society, it was posted on the official IEEE-SSCS vTools workshop site on 21 July 2018, at :
The event was also reported to the IEEE Solid State Circuit Society Magazine as: SSCS Romania Chapter Welcomes Distinguished Lecturer Iire Srinivasulu, IEEE Senior Member, during a Round Table co-organized by the IEEE-ECAI'2018 Conference, editorial written by Chairman - C. Ravariu and was accepted for publication in Dec. - 2018. Here are picked some photos from the event, from IEEE SSCS Magazine.
Fig . The audience of Prof. Srinivasulu’s lecture consisted of students, professors, and people from industry and meet the SSCS037 Romanian Chair in Iasi (in IEEE Solid State Circuit Society Magazine).