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Demonstrator Fabrication in Planar Technology of a Tunneling Transistor through Ultra-thin Insulators - A Promotor of a Nanodevices Series and Industrial Usefulness Emphasis

Coordinated by: Cristian Ravariu

Other department members involved in this project: Florin Babarada, Lidia Dobrescu

Other persons involved in the project

  • CP I Elena Manea
  • CP I Purica Munizer
  • CP I Ileana Cernica
  • CP I Adrian Dinescu
  • CP II Ioana Pachiu
  • Resp. econ. Alina Popescu
  • CP III Cătălin Pârvulescu
  • Drd. Vlad Plăcintă

Description:

UEFISCDI Code: PN-III- P2-2.1- PED-2016- 0427
Project type: Experimental Demonstrative Project
Contract no: 205PED / 2017
Period: August 2017 - December 2018
Coordinator: UPB
Partner: IMT-Bucharest

Abstract: The main objective of this project is the fabrication of an electronic device prototype based on the ultra-thin insulator tunneling, as the first exponent on Silicon wafer of the so called Nothing On Insulator (NOI) transistor, as planar variant. For p-NOI, the insulator can be vacuum or oxide and is important to be ultra-thin of 2...10nm thickness. We propose in this project a planar p-NOI architecture, achievable in the Si-technology, with oxide as insulator. The practical relevance of the project derives from a fabricated p-NOI device in multiple variants and the matching between experimental, theoretical and simulated curves. So that the future Atlas simulations to be anchored in a real technology. This obvious step of a p-NOI exponent fabrication was clearly demanded by the last reviewers from IEEE Transaction on Electron Devices and VLSI. The technical-scientific novelty and feasibility derive from: new device implementation by a well-controlled Si- planar technology, preliminary p-NOI variant already simulated in Atlas in this proposal and intermediary steps in the project plan (masks design and simulations, masks fabrication ~ intermediary steps for fabrication). The project management concerns the product management scheme.The experience of both teams - UPB- IMT, also demonstrated in previous common research projects and publishing, is a favorable reason to ensure the project scope and feasibility.

General Scopes:

O1. Design and simulation of the NOI variants, in different configurations; 
O2. Design of the technology for the p-NOI variants implementations in Si-planar technology; 
O3. Masks design &amp; fabrication for p-NOI variants on Si-wafer; 
O4. Fabrication of the p-NOI variants in the Si-planar technology; 
O5. Electrical tests and characterization of p-NOI fabricated variants; 
O6. Demonstration the ID-VD tunneling in fabricated p-NOI, by experimental measurements; 
O7. Searching for industrial applications, patent, formulation of conclusions; 
O8. Disseminations, technical meetings.

Scientific results per project

  1. selection of p-NOI device variants to be constructed in Si-planar technology;
  2. functional validation by Atlas-Athena simulations;
  3. designing of the technological steps and masks for p-NOI;
  4. production of the p-NOI masks set.
  5. the practical result of the technological flow in Silicon for p-NOI variants;
  6. practical products made as variants of p-NOI (NOI in planar technology);
  7. the material and process characterization results;
  8. the static and dynamic characterizations of manufactured p-NOI results;
  9. financial and scientific reports per steps;
  10. results as published articles and dissemination in national / international scientific forums;
  11. submission of 1 patent to OSIM.

Start Stages

  • Stage I. Design and simulation of the p-NOI variants aided by soft-hard tools
  • Stage II. Fabrication of the p-NOI variants, assisted by microelectronics tools from Si-technology