Assistant Professors < Back

Coordinates the courses: Compilers for HW Designers, Computer Programming, Data Structures and Algorithms, Object Oriented Programming, Software Development Process and Testing

Coordinates the laboratories: Computer Programming, Data Structures and Algorithms, Electronic Circuits (Digital), Software Development Tools

Publications

2018

  1. Datcu Octaviana, Hobincu Radu, Petrica Lucian, "Dynamically changing the secret key of an FPGA chaos-based cipher", ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, Vol. 21, pp. 18-33, Publisher: EDITURA ACAD ROMANE, WOS:000433876800002, 2018, [Article]

2017

  1. Datcu Octaviana, Hobincu Radu, Petrica Lucian, "Baptista's Chaos-Based Cipher Implemented in a Field Programmable Gate Array", 2017 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), 40TH EDITION, pp. 191-194, Publisher: IEEE, WOS:000425844500040, 2017, [Proceedings Paper]

2016

  1. Gheolbanoiu Alexandru, Popescu Vlad, Hobincu Radu, Petrica Lucian, "A SOFTWARE-DEFINED FPGA VECTOR PROCESSOR WITH APPLICATION-AWARE RECONFIGURATION", UNIVERSITY POLITEHNICA OF BUCHAREST SCIENTIFIC BULLETIN SERIES C-ELECTRICAL ENGINEERING AND COMPUTER SCIENCE, Vol. 78, pp. 43-56, Publisher: POLYTECHNIC UNIV BUCHAREST, WOS:000393328400004, 2016, [Article]
  2. Stefan Gheorghe M., Bira Calin, Hobincu Radu, Malita Mihaela, "FPGA-Based Programmable Accelerator for Hybrid Processing", ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, Vol. 19, pp. 148-165, Publisher: EDITURA ACAD ROMANE, WOS:000399549500012, 2016, [Article]
  3. GHEOLBANOIU, Alexandru, MOCANU, Dan, "Global Feedback Self-Programmable Cellular Automaton Random Number Generator", Revista Tecnica De La Facultad De Ingenieria Universidad Del Zulia, Volume 39, Issue 1, , pp. 1-9, None, 2016, [None]

2014

  1. GHEOLBĂNOIU, Alexandru, MOCANU, Dan, "Cellular Automaton pRNG with a Global Loop for Non-Uniform Rule Control",

    18th International Conference on Circuits, Systems, Communications and Computers (CSCC)

    , pp. 415-420, None, 2014, [None]
  2. CODREANU, Valeriu, COȚOFANĂ, Sorin, "Energy-Efficient Computation of L1 and L2 Norms on a FPGA SIMD Accelerator, with Applications to Visual Search",

    18th International Conference on Circuits, Systems, Communications and Computers (CSCC)

    , pp. 432-437, None, 2014, [None]

2013

  1. Bira Calin, Petrica Lucian, Hobincu Radu, "OPINCAA: A Light-Weight and Flexible Programming Environment For Parallel SIMD Accelerators", ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, Vol. 16, pp. 336-350, Publisher: EDITURA ACAD ROMANE, WOS:000336723900006, 2013, [Article]
  2. , "OPINCAA: A Light-Weight and Flexible Programming Environment For Parallel SIMD Accelerators",

    Romanian Journal of Information Science and Technology

    , pp. 336-350, None, 2013, [None]

2012

  1. CODREANU, Valeriu, "GNU Compiler Collection Backend Port for the Integral Parallel Architecture",

    UBP Bulletin

    , pp. 79-92, None, 2012, [None]

2011

  1. CODREANU, Valeriu, "Increasing vector processor pipeline efficiency with a thread-interleaved controller",

    15th International Conference on System Theory, Control, and Computing (ICSTCC)

    , pp. 1 - 4, None, 2011, [None]

2010

  1. Codreanu Valeriu, Hobincu Radu, "Performance Gain from Data and Control Dependency Elimination in Embedded Processors", 2010 9TH INTERNATIONAL SYMPOSIUM ON ELECTRONICS AND TELECOMMUNICATIONS (ISETC), pp. 47-50, Publisher: IEEE, WOS:000296356700009, DOI:10.1109/ISETC.2010.5679319, 2010, [Proceedings Paper]
  2. BUMBĂCEA, Petronela, CODREANU, Valeriu, "Integral Parallel Architecture in System-on-Chip Designs",

    CAS 2010 Proceedings, vol.1

    , pp. 35-42, None, 2010, [None]
  3. BUMBĂCEA, Petronela, CODREANU, Valeriu, "Technology Driven Architecture for Integral Parallel Embedded Computing CAS 2010 Proceedings, vol.1, pag.35-42.",

    CAS 2010 Proceedings, Volume 1

    , pp. pag.35-42., None, 2010, [None]
  4. Bumbacea Petronela, Codreanu Valeriu, Hobincu Radu, Petrica Lucian, Stefan Gheorghe M., "TECHNOLOGY DRIVEN ARCHITECTURE FOR INTEGRAL PARALLEL EMBEDDED COMPUTING", 2010 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), VOLS 1 AND 2, pp. 35-42, Publisher: IEEE, WOS:000371396100005, 2010, [Proceedings Paper]

Degrees

  • November 1, 2008 - October 31, 2011: University Politehnica of Bucharest, Faculty of Electronics, Telecommunication and Information Technology - PhD.
  • October 1, 2003 - June 30, 2008: University Politehnica of Bucharest, Faculty of Electronics, Telecommunication and Information Technology - Electronic Engineer, Opto-electronics specialization, Microelectronics section.

Professional Experience

  • November 11, 2012 - October 13, 2014 : Ixia Romania, Senior Java Engineer with Ixia, I was responsible for implementing software solutions for controlling network equipment.
  • October 1, 2012 - present: Teaching assistant at University Politehnica of Bucharest, Department of Electronics, Telecommunication and Information Technology, teaching Digital Integrated Circuits, Object Oriented Programming and Data Structures and Algorithms.
  • October 1, 2006 - September 30, 2012: University Politehnica of Bucharest, Department of Electronics, Telecommunication and Information Technology, Network Administrator Engineer with DCAE department, I also worked at improving the teaching process in the department by creating new laboratory platforms, configuring the infrastructure, creating new evaluation tests, updating the website and contributing to the Wikilabs. During this time, I also taught Integrated Digital Circuits and Object Oriented Programming labs for undergraduate students, and Advanced Digital Systems for master students.
  • December 1, 2011 - April 30, 2012: Software Engineer at S.C. Mobitelco S.R.L., I was responsible with developing a library and a software simulator for Software Defined Radio, in C++.
  • January 15, 2008 - August 1, 2009: Delphi programmer at UbiCORE Technology in collaboration with the German company Softtech, I was responsible with developing plugins to import and export IFC (Industry Foundation Classes) files for the Spirit CAD application.
  • October 1, 2005 - January 15, 2008: Junior Engineer at ubiCORE Technology, I was responsible with developing and testing software for a Java processor called ObjectCORE, including unit tests, instruction level simulator, cross-compiler and micro-kernel, as well as hardware design for the processor's cache controller.

Academic Activity

My current interests include software design for quality of life applications and research in bioinformatics algorithms and performance computing.